View K4S281633D-N1H_41579.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Preliminary
K4S281633D-RL(N)
CMOS SDRAM
8Mx16 SDRAM 54CSP
(VDD/VDDQ 3.0V/3.0V & 3.3V/3.3V)
Revision 0.6 November 2001
Rev. 0.6 Nov. 2001
Preliminary
K4S281633D-RL(N)
Revision History
Revision 0.0 (February 21. 2001, Target)
CMOS SDRAM
* First generation of 128Mb Low Power SDRAM without special function (V DD 3.0V, VDDQ 3.0V)
Revision 0.1 (June 4. 2001, Target)
* Addition of DC Current value.
Revision 0.2 (June 20. 2001, Target)
* Changed device name from low power sdram to mobile dram.
Revision 0.3 (August 1. 2001, Target)
* Change of tSAC from 6ns to 6.5ns in case of -1L part, from 7ns to 7.5ns in case of -15 part. * Change of tOH from 3ns to 3.5ns. * Change V IH min. from 2.0 V to 0.8xVDDQ and VOH min. from 2.4V to 0.9xVDDQ.
Revision 0.4 (October 6. 2001, Preliminary)
* Changed DC current. * Changed of CL2 tSAC from 6ns to 7ns and CL3 tSAC from 6.5ns to 7ns for -75 part. * Changed of CL2 tSAC from 6.5ns to 8ns and CL1 tSAC from 18ns to 20ns for -1L part. * Changed of tOH from 3ns to 2.5ns. * Changed of tSS from 2.5ns to 2.0ns for -75 part and from 3.0ns to 2.5ns for -1L part. * Integration of VDDQ 1.8V device and 2.5V device. * Changed VIH min. from 0.8xVDDQ to 0.9xVDDQ and VOH min. from 0.9xVDDQ to 0.95xVDDQ. * Changed VIL max. from 0.8V to 0.3V and VOL min. from 0.4V to 0.2V. * Changed IOH from -0.1mA to -2mA and IOL from 0.1mA to 2mA. * Erased -15 bin and added -1H bin.
Revision 0.5 (October 12. 2001, Preliminary)
* Changed VIH min. from 0.9xVDDQ to 2.0V and VOH min. from 0.95xVDDQ to 2.4V. * Changed VIL max. from 0.3V to 0.8V and VOL min. from 0.2V to 0.4V.
Revision 0.6 (November 7. 2001, Preliminary)
* Changed VIH min. from 2.0V to 2.2V and VIL max. from 0.8V to 0.5V.
Rev. 0.6 Nov. 2001
Preliminary
K4S281633D-RL(N)
2M x 16Bit x 4 Banks SDRAM in 54CSP
FEATURES
* 3.0V & 3.3V power supply. * LVTTL compatible with multiplexed address. * Four banks operation. * MRS cycle with address key programs. -. CAS latency (1 & 2 & 3). -. Burst length (1, 2, 4, 8 & Full page). -. Burst type (Sequential & Interleave). * All inputs are sampled at the positive going edge of the system clock. * Burst read single-bit write operation.. * DQM for masking. * Auto refresh. * 64ms refresh period (4K cycle). * Commercial Temperature Operation (-25C ~ 70 C). Extended Temperature Operation (-25C ~ 85C). K4S281633D-RL/N75 K4S281633D-RL/N1H
CMOS SDRAM
GENERAL DESCRIPTION
The K4S281633D is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits, fabricated with SAMSUNGs high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock and I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
ORDERING INFORMATION
Part No. Max Freq. 133MHz(CL=3) 100MHz(CL=2) 100MHz(CL=2)
*1
Interface Package
LVTTL
54 CSP
K4S281633D-RL/N1L 100MHz(CL=3)
-RN ; Low Power, Operating Temperature : -25'C~85'C. -RL ; Low Power, Operating Temperature : -25'C~70'C.
FUNCTIONAL BLOCK DIAGRAM
Note : 1. In case of 40MHz Frequency, CL1 can be supported.
I/O Control
LWE
Data Input Register
LDQM
Bank Select 2M x 16 Sense AMP 2M x 16 2M x 16 2M x 16
Refresh Counter
Output Buffer
Row Decoder
Row Buffer
DQi
Address Register
CLK ADD
Column Decoder Col. Buffer Latency & Burst Length
LRAS
LCBR
LCKE LRAS LCBR LWE LCAS
Programming Register LWCBR LDQM
Timing Register
CLK
CKE
CS
RAS
CAS
WE
LDQM
UDQM
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 0.6 Nov. 2001
Preliminary
K4S281633D-RL(N)
Package Dimension and Pin Configuration
< Bottom View*1 >
E1
CMOS SDRAM
< Top View*2 >
54Ball(6x9) CSP
9 A B C D1 D E F G H J
8
7
6
5
4
3
2
1 e
1 A B C D E F G H J
D/2 D
2 DQ15 DQ13 DQ11 DQ9 NC CLK A11 A7 A5
3 VSSQ VDDQ VSSQ VDDQ VSS CKE A9 A6 A4
7 VDDQ VSSQ VDDQ VSSQ VD D CAS BA0 A0 A3
8 DQ0 DQ2 DQ4 DQ6 LDQM RAS BA1 A1 A2
9 VD D DQ1 DQ3 DQ5 DQ7 WE CS A10 VD D
VSS DQ14 DQ12 DQ10 DQ8 UDQM NC A8 VSS
E E/2
Pin Name CLK
Pin Function System Clock Chip Select Clock Enable Address Bank Select Address Row Address Strobe Column Address Strobe Write Enable Data Input/Output Mask Data Input/Output Power Supply/Ground Data Output Power/Ground
*2: Top View
CS CKE A0 ~ A 11
A A1
BA0 ~ BA1 RAS CAS WE L(U)DQM DQ 0 ~ 15 VDD /VSS VDDQ/VSSQ
Max. 0.20
Encapsulant
b
*1: Bottom View < Top View*2 >
#A1 Ball Origin Indicator
SAMSUNG WEEK
K4S281633D-RL(N)
[Unit:mm] Symbol A A1 E E1 D D1 e b Min 0.90 0.30 0.40 Typ 0.95 0.35 8.00 6.40 8.00 6.40 0.80 0.45 Max 1.00 0.40 0.50 0.08
Rev. 0.6 Nov. 2001
Preliminary
K4S281633D-RL(N)
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to Vss Voltage on V D D supply relative to Vss Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD , VDDQ TSTG PD IOS Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +150 1 50
CMOS SDRAM
Unit V V C W mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, T =-25C ~ 70 C (Commercial), -25 C ~ 85C (Extended)) A Parameter Supply voltage Input logic high voltage Input logic low voltage Output logic high voltage Output logic low voltage Input leakage current Symbol VD D VDDQ VIH VIL VOH VOL ILI Min 2.7 2.7 2.2 -0.3 2.4 -10 Typ 3.0 3.0 3.0 0 Max 3.6 3.6 VDDQ+0.3 0.5 0.4 10 Unit V V V V V V uA 1 2 IOH = -2mA IOL = 2mA 3 Note
Note : 1. VIH (max) = 5.3V AC. The overshoot voltage duration is 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V VIN VDDQ. Input leakage currents include HI-Z output leakage for all bi-directional buffers with Tri-State outputs. 4. Dout is disabled, 0V VOUT VDDQ.
CAPACITANCE
Clock
(VDD = 3.0V, TA = 23C, f = 1MHz, V REF =0.9V 50 mV) Pin Symbol CCLK CIN CADD COUT Min 2.0 2.0 2.0 3.5 Max 4.0 4.0 4.0 6.0 Unit pF pF pF pF Note
RAS, CAS, WE, CS, CKE, DQM Address D Q0 ~ DQ15
Rev. 0.6 Nov. 2001
Preliminary
K4S281633D-RL(N)
DC CHARACTERISTICS
Parameter
CMOS SDRAM
Recommended operating conditions (Voltage referenced to VSS = 0V, TA =-25C ~ 70C (Commercial), -25C ~ 85 C (Extended)) Symbol Burst length = 1 tRC tR C(min) IO = 0 mA CKE VIL(max), tCC = 10ns Test Condition -75 Operating Current (One Bank Active) Precharge Standby Current in power-down mode ICC1 80 Version -1H 75 -1L 75 mA 1 Unit Note
ICC2P
0.5 0.5 12
ICC2PS CKE & CLK VIL(max), tCC = ICC2N CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL (max), tCC = Input signals are stable CKE VIL(max), tCC = 10ns
mA
Precharge Standby Current in non power-down mode ICC2NS Active Standby Current in power-down mode ICC3P
mA 10 7 7 23 mA
ICC3PS CKE & CLK VIL(max), tCC = ICC3N CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL (max), tCC = Input signals are stable IO = 0 mA Page burst 4Banks Activated tCCD = 2CLKs tRC tR C(min) CKE 0.2V -RL -RN
mA
Active Standby Current in non power-down mode (One Bank Active)
ICC3NS
20
mA
Operating Current (Burst Mode) Refresh Current Self Refresh Current
ICC4
130
130
110
mA
1
ICC5 ICC6
170
170 500
155
mA uA uA
2 3 4
Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. K4S281633D-RL** 4. K4S281633D-RN** 5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ)
Rev. 0.6 Nov. 2001
Preliminary
K4S281633D-RL(N)
AC OPERATING TEST CONDITIONS
Parameter AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition
VDDQ
CMOS SDRAM
(VDD = 2.7V ~ 3.6V, TA =-25C ~ 70C (Commercial), -25 C ~ 85 C (Extended)) Value 2.4 / 0.4 0.5 x VDDQ tr/tf = 1/1 0.5 x VDDQ See Fig. 2
Vtt = 0.5 x VDDQ
Unit V V ns V
1200 Output 870 VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA 30pF Output Z0 = 50
50
30pF
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted) Parameter Row active to row active delay RAS to CAS delay Row precharge time Row active time Row cycle time Last data in to row precharge Last data in to Active delay Last data in to new col. address delay Last data in to burst stop Col. address to col. address delay Symbol - 75 tRRD (min) tRCD (min) tRP(min) tRAS(min) tRAS(max) tR C(min) tRDL(min) tDAL (min) tCDL(min) tBDL (min) tCCD (min) CAS latency=3 Number of valid output data CAS latency=2 CAS latency=1 65 15 20 20 45 Version -1H 20 20 20 50 100 70 2 2 CLK + tRP 1 1 1 2 1 0 ea 4 84 -1L 20 24 24 60 ns ns ns ns us ns CLK CLK CLK CLK 2 2 3 1 2 1 1 1 1 Unit Note
Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop.
Rev. 0.6 Nov. 2001
Preliminary
K4S281633D-RL(N)
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter CAS latency=3 CLK cycle time CAS latency=2 CAS latency=1 CAS latency=3 CLK to valid output delay CAS latency=2 CAS latency=1 CAS latency=3 Output data hold time CAS latency=2 CAS latency=1 CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CAS latency=3 CLK to output in Hi-Z CAS latency=2 CAS latency=1 tSHZ tC H tC L tSS tSH tSLZ tOH 2.5 2.5 2.5 2.5 2.0 1.0 1 5.4 7 tSAC tC C Symbol Min 7.5 10 5.4 7 2.5 2.5 3 3 2.5 1.5 1 7 7 1000 - 75 Max Min 10 10 7 7 2.5 2.5 2.5 3 3 2.5 1.5 1 1000 -1H Max Min 10 12 25 -1L
CMOS SDRAM
Unit Max
Note
1000
ns
1
7 8 20 ns 1,2
ns
2
ns ns ns ns ns 7 8 20 ns
3 3 3 3 2
Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Rev. 0.6 Nov. 2001
Preliminary
K4S281633D-RL(N)
SIMPLIFIED TRUTH TABLE
COMMAND Register Mode Register Set Auto Refresh Refresh Entry Self Refresh Exit
CKEn-1 CKEn CS RAS CAS WE DQM BA0,1
CMOS SDRAM
A10 /AP A11, A9 ~ A 0 Note
H H
X H L H X X
L L L H L L
L L H X L H
L L H X H L
L H H X H H
X X
OP CODE X
1, 2 3 3 3 3
L H H
X X X V V
X Row Address L H L
Column Address (A0~ A8) Column Address (A0~ A8)
Bank Active & Row Addr. Read & Column Address Write & Column Address Burst Stop Precharge Bank Selection All Banks Entry Exit Entry Precharge Power Down Mode Exit DQM No Operation Command Auto Precharge Disable Auto Precharge Enable Auto Precharge Disable Auto Precharge Enable
4 4, 5 4 4, 5 6
H H H
X X X
L L L H L X H L H L
H H L X V X X H X V X
L H H X V X X H X V
L L L X V X X H X V
X X X
V
H X
V X
L H
X
Clock Suspend or Active Power Down
H L H
L H L
X X X
X
X X V X X 7
L H H
H
X
H L
X H
X H
X H
X
(V=Valid, X=Dont Care, H=Logic High, L=Logic Low) Note : 1. OP Code : Operand Code A0 ~ A 11 & BA0 ~ BA1 : Program keys. (@MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are the same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A 10 /AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at the positive going edge of CLK masks the data-in at that same CLK in write operation (Write DQM latency is 0), but in read operation makes the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2).
Rev. 0.6 Nov. 2001
Preliminary
K4S281633D-RL(N)
MODE REGISTER FIELD TABLE TO PROGRAM MODES
Register Programmed with Normal MRS Address Function BA0 ~ BA1*1 "0" Setting for Normal MRS A11 ~ A10/AP RFU A9 W.B.L A8 A7 A6 A5 CAS Latency A4 A3 BT
CMOS SDRAM
A2
A1 Burst Length
A0
Test Mode
Normal MRS Mode
Test Mode A8 0 0 1 1 A7 0 1 0 1 Type Mode Register Set Reserved Reserved Reserved A6 0 0 0 0 1 1 1 1 CAS Latency A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 Latency Reserved 1 2 3 Reserved Reserved Reserved Reserved 0 0 Setting for Normal MRS BA1 A3 0 1 Burst Type Type Sequential Interleave Mode Select BA0 Mode A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 Burst Length A0 0 1 0 1 0 1 0 1 BT=0 1 2 4 8 BT=1 1 2 4 8
Write Burst Length A9 0 1 Length Burst Single Bit
Reserved Reserved Reserved Reserved Reserved Reserved Full Page Reserved
Full Page Length : 256(x16)
Power Up Sequence
1. Apply power and start clock, Attempt to maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs. 2. Power is applied to VDD and VDDQ (simultaneously). 3. Maintain stable power, stable clock and NOP input condition for a minimum of 200us. 4. Issue precharge commands for all banks of the devices. 5. Issue 2 or more auto-refresh commands. 6. Issue a mode register set command to initialize the mode register.
Note : 1. In order to assert normal MRS, BA0 and BA1 should set "0" absolutely.
Rev. 0.6 Nov. 2001

▲Up To Search▲

Price & Availability of K4S281633D-N1H

	To Download K4S281633D-N1H Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .